£52,253 to £60,834 per annum This is a fixed term position for 2 years due to time limited funding from an external grant. Overall purpose: To lead the deployment, scaling and maintenance of machine learning systems
About Huawei Research and Development UK Limited Founded in 1987, Huawei is a leading global provider of information and communications technology (ICT) infrastructure and smart devices. We have 207,000 employees and operate in over 170 countries
NVIDIA is seeking engineers to develop algorithms and optimizations for our LPX inference and compiler stack. You will work at the intersection of large-scale systems, compilers, and deep learning, crafting how neural network workloads map onto future
CPU RTL Design Engineer (Staff) A fantastic opportunity for an experienced RTL Design Engineer to join a global leader in semiconductors, working alongside their CPU Team in Cambridge (UK). About the Role Working on CPU RTL development targeted
£45,869 to £51,547 per annum Overall purpose: You will support the Estates and Facilities (E&F) Manager and Deputy Chief Operating Officer by ensuring that the buildings occupied by the MRC Laboratory of Molecular Biology (LMB) on
Principal Kernel Engineer A global Tech leader in ICT infrastructure and R&D Giant is hiring a Principal Kernel Engineer to join their specialized team in Cambridge . In this role, you will drive deep kernel performance and power
Fixed term 2 years We are seeking a Machine Learning Engineer specialising in deployment and infrastructure to support large-scale connectomics within the group of Dr Albert Cardona at the MRC Laboratory of Molecular Biology. The role will
£52,253 to £60,834 per annum This is a fixed term position for 2 years due to time limited funding from an external grant. Overall purpose: To lead the deployment, scaling and maintenance of machine learning systems
Role Overview As a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team of engineers passionate about designing industry-leading CPU cores based on the revolutionary open‑source RISC‑V architecture. Responsibilities Architect, design and implement new
Responsibilities Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel. Integrate new design content into SiFives Chisel/FIRRTL framework and contribute to improvements to that framework to enable
Staff/Senior Staff RTL Design Engineer – CPU This is an exceptional opportunity to join a global pioneer in next-generation processor technology. My client is a leading semiconductor company at the forefront of CPU innovation, developing advanced compute
Job Description As a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores, based on the revolutionary open‑source RISC‑V architecture. Responsibilities Architect, design and
Oversee system design and take a leading role. Location & Compensation Cambridge, hybrid work; salary up to £80,000 (DOE). Overview This US tech firm’s Cambridge R&D office uses dynamic, high‑speed FPGA RTL logic to execute automated
TidalSense is a respiratory technology company with a mission to transform the diagnosis, monitoring and management of chronic respiratory conditions, such as asthma and COPD. The company has ambitions to enable a population-scale change in respiratory
Job Summary We are seeking a visionary and technically accomplished Senior Principal CPU Architect based in Cambridge, England, to lead the definition, modeling, and co‑design of next‑generation high‑performance CPU architectures. In this highly strategic role, you
What if you could shape a career as unique as you? At WSP, you can always find opportunities to grow and do what matters to you. Make the most of our global reach to discover new
What if you could do the kind of work the world needs? At WSP, you can access our global scale, contribute to landmark projects and connect with the brightest minds in your field to do the