Company:Qualcomm Technologies International Ltd Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: Job Overview Qualcomm is seeking talented Physical Design Engineers to join the Nuvia CPU team in Cambridge, UK. The team is developing next-generation,
Job Overview Qualcomm Technologies International Ltd is seeking talented Physical Design Engineers to join the Nuvia CPU team in Cambridge, UK. The team develops next‑generation, high‑performance, power‑efficient custom CPU cores for advanced compute and server‑class platforms.
About Us Axelera AI is not your regular deep‑tech startup. We are creating the next‑generation AI platform to support anyone who wants to help advancing humanity and improve the world around us. In just four years,
Senior Engineer – Silicon Physical Design (Italy based) Join or sign in to find your next job Join to apply for the Senior Engineer – Silicon Physical Design (Italy based) role at Axelera AI About Us:
A pioneering company in AI and semiconductor solutions, is seeking a highly skilled Senior Physical Design Engineer to contribute to the development of advanced multi-core in-memory compute SoCs. This role offers the chance to work on
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of
CPU Physical Design Engineer (Senior & Staff) - Multiple Headcount - Cambridge (Onsite) About the Role Join our world-class CPU team in Cambridge to build next-generation, high-performance, power-efficient custom CPU cores for advanced compute and server
European Tech Recruit in Cambridge is seeking a Senior/Staff CPU Physical Design Engineer to lead high‑performance CPU cores from RTL to GDSII, focusing on timing closure, power integrity, and PD automation. The role requires hands‑on CPU