Company:Qualcomm Technologies International Ltd Job Area:Engineering Group, Engineering Group Hardware Engineering General Summary: The Test Development Engineer is responsible for pre and post silicon validation of Qualcomm IPs, ensuring they meet new product introduction milestones and are
Teamwork makes the stream work. Roku is changing how the world watches TV Roku is the #1 TV streaming platform in the U.S., Canada, and Mexico, and weve set our sights on powering every television in
Contract Type: Full-time, Permanent Location: Cambridge, UK Closing date for applications: Monday 17th August 2026 at 1pm (UK time). Visa Sponsorship available Join Nu Quantum - Shaping the Future of Technology Nu Quantum is at the forefront
Role Overview As a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team of engineers passionate about designing industry-leading CPU cores based on the revolutionary open‑source RISC‑V architecture. Responsibilities Architect, design and
Job Description This role requires expertise in RTL design, formal testing, and cross‑team collaboration to support SiFive’s advanced RISC‑V platforms. Responsibilities Specify, design and implement new arithmetic operators for arithmetic RISC‑V instructions, including floating‑point, vector, crypto
# Senior ALU Design EngineerApplylocations: Cambridge, England, United Kingdomtime type: Full timeposted on: Posted Todayjob requisition id: R- # About SiFive *As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of
Responsibilities Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel. Integrate new design content into SiFives Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic
Job Description As a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores, based on the revolutionary open‑source RISC‑V architecture. The role
Job Description As a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores, based on the revolutionary open‑source RISC‑V architecture. Responsibilities Architect,
Description Join our innovative team developing next-generation silicon solutions for Amazons consumer devices, Ring and Blink. We are seeking a collaborative Design Verification Engineer years of industry experience to help create energy-efficient System-on-Chip (SoC) designs. You