About SiFiveAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world.
Overview In this role you will architect and implement new RISC-V core features using Chisel, drive performance and power optimizations, and integrate work into SiFive’s Chisel/FIRRTL framework. You will verify designs, collaborate with verification and physical
Senior RTL Design Engineer - CPU page is loaded# Senior RTL Design Engineer - CPUlocations: Cambridge, England, United Kingdomtime type: Full timeposted on: Posted Todayjob requisition id: R- # About SiFive *As the pioneers who introduced
Job Description As a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores, based on the revolutionary open‑source RISC‑V architecture. Responsibilities Architect,
Overview In this role you will design and evolve high-performance RISC-V CPU cores, contributing to SiFive’s open-source hardware IP. You’ll work across design, verification, and physical implementation to deliver optimized cores and ISA extensions. You’ll collaborate
About SiFiveAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s
About SiFiveAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s