At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational
Role Overview As a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team of engineers passionate about designing industry-leading CPU cores based on the revolutionary open‑source RISC‑V architecture. Responsibilities Architect, design and
Responsibilities Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel. Integrate new design content into SiFives Chisel/FIRRTL framework and contribute to improvements to that framework to enable
Staff/Senior Staff RTL Design Engineer – CPU This is an exceptional opportunity to join a global pioneer in next-generation processor technology. My client is a leading semiconductor company at the forefront of CPU innovation, developing advanced
Job Description As a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores, based on the revolutionary open‑source RISC‑V architecture. The role
Job Description As a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores, based on the revolutionary open‑source RISC‑V architecture. Responsibilities Architect,
Senior RTL Design Engineer – CPU This is an exceptional opportunity to join a global pioneer in next‑generation processor technology. My client is a leading semiconductor company at the forefront of CPU innovation, developing advanced compute