Company:Qualcomm Technologies International Ltd Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: We are seeking a senior-level Low Power MSIC-Analog System Technologist with deep expertise in mixed-signal IC and system design and a proven record
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the worlds top consumer brands. Cirrus Logic
Overview Join Microsoft Research Cambridge to invent optical interconnects that deliver power efficient and reliable with optical IO links. Department/Organization/Location: Microsoft Research Cambridge (Cambridge, UK), working with researchers and partner engineering teams on next-generation optical I/O
About The Role and TeamQuantum Motion is a fast-growing quantum computing scale-up based in London. We are developing quantum processors based on industrial-grade silicon chips, with the potential to radically transform computing power in areas such
⌕ Job Overview: We are looking for a Photonic Layout Engineer to join our Photonics team and contribute to the physical design, verification and development of advanced integrated photonic devices. You will work closely with engineers
The Head of Foundry owns fabrication reality. This role exists to ensure that what we design can actually be fabricated at yield, at scale, and without surprises. The role As Head of Foundry, you are accountable
About The Role and Team As aStaff/Senior QPU Layout Engineer, you will drive the physical implementation and verification for a cutting-edge quantum processor platform. You’ll be a go-to expert for full-chip and block-level layouts, ensuring designs
We are seeking a Senior RF IC Design Engineer to join our expanding high‑tech client based in Cardiff. Very flexible / hybrid working is available. Following a period of strong success, our client has secured several
Job Title: Senior Layout Engineer Location: Swindon (On-Site Working) Salary: £55,000 - £65,000 + Bonus & Benefits (Depending on Experience) Please Note: All Applicants must have the right to work in the UK without the need
Own the design and simulation activity of key passive and active components within the Oriole PDK Lead the design customisation of high performance key photonic building blocks within a commercial foundry PDK Work collaboratively within the Oriole PIC
Infrastructure Engineer Cambridge, UK Start date: September 2026 or ASAP Contract: Permanent, full-time role About us At Wave Photonics, we are building a platform to enable and accelerate the development, mass production and adoption of integrated
Oriole Photonics in the United Kingdom seeks a senior Photonics Design Lead to own the design and simulation of key passive and active components within the Oriole PDK, and to lead customization of high performance photonic building
Infrastructure Engineer Cambridge, UK Start date: September 2026 or ASAP Contract: Permanent, full-time role About us At Wave Photonics, we are building a platform to enable and accelerate the development, mass production and adoption of integrated
Quantum is now, and its built here. Oxford Ionics, now part of IonQ, is pioneering the next generation of quantum computing. Using our world-leading trapped-ion technology, were building the most powerful, accurate and reliable quantum systems
Job Title : Senior Layout Engineer Location : Swindon (On-Site Working) Salary : £55,000 - £65,000 + Bonus & Benefits (Depending on Experience) Please Note : All Applicants must have the right to work in the
Overview Join Microsoft Research Cambridge to invent optical interconnects that deliver power efficient and reliable with optical IO links. Department/Organization/Location: Microsoft Research Cambridge (Cambridge, UK), working with researchers and partner engineering teams on next-generation optical I/O
Company:Qualcomm Technologies International LtdJob Area:Engineering Group, Engineering Group ASICS EngineeringGeneral Summary:We are seeking a senior-level Low Power MSIC-Analog System Technologist with deep expertise in mixed-signal IC and system design and a proven record of chip-level technical